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IR3710MTRPBF
Gate Impedance:
We recommended placing LGATE signal path on top
next to the source of low side MOSFET path and
place UGATE signal path on top of PHASE signal
path.
If the connection of PGND pin to the source of low
side MOSFET is through an internal layer, it is
recommended connecting through at least 2 vias by
build a small island of next to PGND pin.
Power Stage:
Figure 24 shows the flowing current path for on and
off period. The on time path has low average DC
current with high AC current. Therefore, it is
recommended to place input ceramic capacitor,
upper and lower MOSFET in a tight loop as shown in
Figure 24. The purpose tight loop of input ceramic
capacitor is to suppress the high frequency (10MHz
range) switching noise to reduce Electromagnetic
Interference (EMI). If this path has high inductance,
the circuit will cause voltage spike and ringing,
increase the switching loss. The off time path has low
AC and high average DC current. Therefore, it is
recommended to layout with tight loop and fat trace
at two end of inductor. The higher resistance of this
loop increases the power loss. The typical resistance
value of 1 ounce copper thickness has one-half mili-
? per square.
Figure 24. Current Path of Power Stage
Page 16 of 20
www.irf.com
IR Confidential
4/26/10
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